List of 7400 series integrated circuits

2,463
dual 2-line to 4-line decoder/demultiplexer with ope6e priority encoder HC/HCT r> > 6 r > <d> <748Qdfull adder9> d> quad 499 >enetd>si>dual J/sn54ls01.pdf" reolector/multiplexer p > shift register/demul-K flip-flop with asynchronous cleard> ram 6 (256×1)>ram 6 ram102d> ram 6 input NAND gate with op2ofollow">HC/follow">HC/oc85 -line to 1-l 6HC/HCT 6 multipe/tr> 6 HC/HCT 748egister/demulnverters with op231ollow">HC/follow">HC/oc85 <>1748egister/demulnverters with op23>multivibra output-of-874154 dual 2wiki/Demultip,buffer/line driver,er/demul-K flip-flop with asynchronous clear-of-874154 ,buffer/line driver,er/demul-K flip-flop with asynchronous clear ,buffer/line driver,er/demulCT138.pdf" rel="24follow">HC/follow">HC/oc85 ofd16ma.org/Ima>46 iki/Ded>74100iki/Ded>74100 mr> d>1 decodHC/HC Xtd> HC/HC 4112 9> si>dual J/sn54ls01.pdf" r2om access memory>enetd>si 741cartr>egister/demulnverters with op2it binary full adder flip-flop CD to decimal decoded> mr> d>1 < (lne dr//e 4d mr> d>1 < (ine drr//e 4d si/dheck>4 74 HC/HCT > HC/follow">HC/oc852 HC/follow">HC/oc85 HC/oc85 HC/HCT> HC/HCT multiplexer -line to de6 ne to de6 > b quad 499 HC/HC d> gered f <>4-bige-trd> <>4-biuffer/line buffeer/demulnverters with op4o low output enable <>4-biuffer/line d buffeer/demulnverters with op4ont/zero/one element <8080ar/demulnverters with op4clusive-or/N element HC/ enable HC/ enable <-to- HC/HCT HC/HCT HC/tor to-1 d> HC/HCT upss=wnt7468 multiplexer > ed> HC/oc85 HC/HCT 1 7457input NAND gate with op51nt/zero/one element si9.org/ si9.org/ si9.org/ne to de6otem-pole>dual 4,4ual 4 pull-upn.csis>si>dual J/sn54ls01.pdf" r5ynchronizer/drivers si9.org/ne to de6otem-pole>dual 4>dual J/sn54ls01.pdf" r5ym access memory si9.org/ne to de HC/HCT ofd4td>74145 6 > ur> ltip gle D-type6 s> 4<>4-bi6ts/data_sheet/745hd>2 s> ts/data_sheet/746iul3_CNV.pdf" rel="463-dynamicogramm ettorg/burso/ood/6l /tsy64K drambi6ts/data_sheet/746i NAND gate with op4it der gle D-type6ts/data_sheet/746i_HCT123.pdf" rel="3im addual 4 /en.wikipedia. gle D-type6ts/data_sheet/746i NAND gate with op53n der l /en.wikipedia. HC/d>si9.org/ne to /td2 HC/o2<16×4) R,a/en.wikipedia. 2 2 quadsrtransAND(EDAC) ltip gle D-type6ts/data_sheet/7463 J/sn54ls01.pdf" r5ync45ntquadsrtransAND/td> /en.wikipedia. erra.quadsrtransAN,a2transtd> <6t NAND gate with op533-3>multid>1 erra.quadsrtransAN,atd> <6t NAND gate with op4it 3>multid>1 erra.quadsrtransAN,altip gle D-type6ts/data_sheet/7463_HCT123.pdf" rel="3im 3>multid>1 erra.quadsrtransAN,atd> ts/data_sheet/746t NAND gate with op53ntollector follow">HC/o5 gle D-type6 HC/o5 gle D-type6 HC/o5 gle D-type6t gle D-type6 HC/o5 ia) Ru/en.wikipedia. gle D-type6 HC/o//toc8d>74157 HC/o//toc8d>74157 > t td2 td2 ltip gle D-type6t > -in serial-e D> gle D-type6> -in serial-e D> e6> 74100 6th 3_CNV.pdf" rel="37>d45ntHC/HCT/ memoryl> 74100 6ble3_CNV.pdf" rel="3er"45ntHC/HCT/ memoryd> > mr> ac"exuld>si>du6 magnitude td>n ac"exuld>si>du6n /r> />74157 > />74157 > /r> />74157 > />74157 > HC/HCT> ip HC/HCT2transtd> 4utsto-1 d> 1 d> 1 d> 1 d> 1 d> ltip gle D-type64145s/td> HC/HCT> ltip gle D-type64145s/td> 4> gle D-type6> 4> > e6> > > dispha/tne elementtd2 < clascd><< clas/na/a> d> RAM4I2 ip netd>se D>>qua/toc85(upsor 9999)e6t< class/MM/MM74C92 text" href="http:36/wCdocuments/data_sheet/74HC_H9ld>2 d> RAM4I2 > uquad4140> uquad4140> 4 < clascd><< class2/16/161779_ text" href="http:541nCdocuments/data_sheet/74HC_H10i_HCT123.pdf" rel="36followry full adori-gle D-tytd> HCtd> ts/data_sheet/7429mul3_CNV.pdf" rel="46e one elemenErra.quadsrtransANecodeTwo-phase flop 1-line data selecErra._detransAN_>qu_dsrtransANenerra.quadsrtransAN4Iwik(EDAC)/td>to-1 d> sORh op53fod>4 /de to-t /de 4 /de < 4 gl //toc8ORh op53fod>4 /de HCd> 4 4 <-a2a-url with asynchrgetr2d> d> ics.nassl<-a2a- elemenL4 d> ics.nas%2Fl4 d> ics.nas%2Fl4 d> ics.nas%2Fl4 /HCT_js("//pry ad2.google> <-ad-cliput="ca-pub-352 63H4al456567" ed><-ad-slot="1662465011etdoins_shscript> (adsbygoogle = nc/t.adsbygoogle || []).push({}); m/divumstyem ce g="dfli/css"t .rcziv5d86d627338hr { margin: 5px; paddl a: 0px; } @mine screeND>qua(min-width: 1201px) { .rcziv5d86d627338hr { qua(min-width: 993px) >qua(max-width: 1200px) { .rcziv5d86d627338hr { qua(min-width: 769px) >qua(max-width: 992px) { .rcziv5d86d627338hr { qua(min-width: 768px) >qua(max-width: 768px) { .rcziv5d86d627338hr { qua(max-width: 767px) { .rcziv5d86d627338hr { 'yarpp-="h12ed yarpp-="h12ed-bine'_shp>No ="h12ed p < care-h>quentDp < ocial-item 11;4bookeum>4flop with asynchr11;4bookus cl carer.php?u=ith asynchrgetr2d> d> ics.nassl (this.flop, ' care-11;4book','left=50,top=50,width=600,height=320,toolbar=0');"re7urn 11lse;eumi4 < ocial-item t4flop with asyt d> ics.nassl (this.flop, ' care-t < ocial-item google_pluseum>4flop with asyplus.googleus cl care?url -phaasynchrgetr2d> d> ics.nassl (this.flop, ' care-google_plus','left=50,top=50,width=600,height=320,toolbar=0');"re7urn 11lse;eumi4 < ocial-item reddlteum>4flop with asyreddltus cl ubmit?url -phaasynchrgetr2d> d> ics.nassl (this.flop, ' care-reddlt','left=50,top=50,width=600,height=320,toolbar=0');"re7urn 11lse;eumi4 < ocial-item whatsappeum>4flop wwhatsappasysend?dfli=L d> ics.nassl (this.flop, ' care-whatsapp','left=50,top=50,width=600,height=320,toolbar=0');"re7urn 11lse;eumi4 < ocial-item p Resteum>4flop with asyp Restus clpin/cre12e/button/?url -phaasynchrgetr2d> d> ics.nassl<=L (this.flop, ' care-p Rest','left=50,top=50,width=600,height=320,toolbar=0');"re7urn 11lse;eumi4 < ocial-item emaileum>4flop wmailto:? ubjd> =L d> ics.nassl (this.flop, ' care-email','left=50,top=50,width=600,height=320,toolbar=0');"re7urn 11lse;eumi4 -td> eumoiudocum/liu <-bpv-p _s dsransAND 4flop with asynchrgetr2d> d> ics.nassauthor/iainhendry" elemenBrowse Author Articd>s"u mspan4 4 _sidb&#wAN with asynchrgetr2d> d> ics.nas" method="get">mlProw"CM> SMDut-/form_,rip /td> mtype>en wit oneflop wit 255PCS Capaci>en wit STMn4 < widget-hav Digetve adKit 280pcs Iow"CMOS Atype PICr/td> < widget-hav Kit + PIC16F877A <-ad-cliput="ca-pub-352 63H4al456567" ed><-ad-slot="7265123767">doins_ shscript> (adsbygoogle = nc/t.adsbygoogle || []).push({}); 4794554826/divu m/divu hdiv4id="/tdfnt-p < widget-havput-icon widget-havput- elem prim1ry-t/ttPri> ml bar-prim1ry-sid2edp d> ics.nas" method="get">mlTag> 7805 widg eveltdmputDBoards Reviewdocu > docu ttci> a widg eveltdmputDBoards Reviewdocu > alevplidg eveltdmputDBoards Reviewdocu > icdocu ttci> icuap docu ttci> p4 Upl-0idg eveltdmputDBoards Reviewdocu > plevp aithifier-0idg eveltdmputDBoards Reviewdocu > eds-0idg eveltdmputDBoards Reviewdocu > td> o/l> icdocu ttci> /td> icdocu ttci> F- el> icvpidg eveltdmputDBoards Reviewdocu > LDRvpidg eveltdmputDBoards Reviewdocu > LM3lip-idg eveltdmputDBoards Reviewdocu > Logic Probep-idg eveltdmputDBoards Reviewdocu > < ma>< :bit photocell < ta>< uredocu ttci> Tuo/ype>ureleogg eveltdmputDBoards Reviewdocu > Wemos review.a/ttPri> < d> ics.nas" method="get">mlSubics.bear name='ge":1flicept- wirst-="utf-8"m1ry Subics.be g- g_subics.nassaidgiderev ar-pridgeSubics.be et">ml

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Part number Units Description Datasheet
7400 4 quad 2-input NAND gate HC/HCT
741G00 1 single 2-input NAND gate HC/HCT
7401 4 quad 2-input NAND gate with open collector outputs LS
741G01 1 single 2-input NAND gate with open drain output
7402 4 quad 2-input NOR gate HC/HCT
741G02 1 single 2-input NOR gate
7403 4 quad 2-input NAND gate with open collector outputs HC/HCT
741G03 1 single 2-input NAND gate with open drain output
7404 6 hex inverter HC/HCT
741G04 1 single inverter
7405 6 hex inverter with open collector outputs HC
741G05 1 single inverter with open drain output
7406 6 hex inverter buffer/driver with 30 V open collector outputs
741G06 1 single inverting buffer/driver with open drain output
7407 6 hex buffer/driver with 30 V open collector outputs
741G07 1 single non-inverting buffer/driver
7408 4 quad 2-input AND gate HC/HCT
741G08 1 single 2-input AND gate
7409 4 quad 2-input AND gate with open collector outputs
741G09 1 single 2-input AND gate with open drain output
7410 3 triple 3-input NAND gate HC/HCT
7411 3 triple 3-input AND gate HC/HCT
7412 3 triple 3-input NAND gate with open collector outputs
7413 2 dual Schmitt trigger 4-input NAND gate
7414 6 hex Schmitt trigger inverter HC/HCT
741G14 1 single Schmitt trigger inverter
7415 3 triple 3-input AND gate with open collector outputs
7416 6 hex inverter buffer/driver with 15 V open collector outputs
7417 6 hex buffer/driver with 15 V open collector outputs
741G17 1 single Schmitt-trigger buffer
7418 2 dual 4-input NAND gate with Schmitt trigger inputs
7419 6 hex Schmitt trigger inverter
7420 2 dual 4-input NAND gate HC/HCT
7421 2 dual 4-input AND gate HC
7422 2 dual 4-input NAND gate with open collector outputs
7423 2 expandable dual 4-input NOR gate with strobe
7424 4 quad 2-input NAND gate gates with Schmitt trigger line-receiver inputs.
7425 2 dual 4-input NOR gate
7426 4 quad 2-input NAND gate with 15 V open collector outputs
7427 3 triple 3-input NOR gate HC/HCT
741G27 1 single 3-input NOR gate
7428 4 quad 2-input NOR buffer
7430 1 8-input NAND gate HC/HCT
7431 6 hex delay elements
7432 4 quad 2-input OR gate HC/HCT
741G32 1 single 2-input OR gate
7433 4 quad 2-input NOR buffer with open collector outputs
7434 6 hex noninverters HC
7435 6 hex noninverters with open-collector outputs
7436 4 quad 2-input NOR gate (different pinout than 7402)
7437 4 quad 2-input NAND buffer
7438 4 quad 2-input NAND buffer with open collector outputs
7439 4 quad 2-input NAND buffer with open collector outputs, input and output terminals flipped, otherwise functionally identical to 7438
7440 2 dual 4-input NAND buffer
7441 1 BCD to decimal decoder/Nixie tube driver
7442 1 BCD to decimal decoder HC/HCT
7443 1 excess-3 to decimal decoder
7444 1 excess-3-Gray code to decimal decoder
7445 1 BCD to decimal decoder/driver
7446 1 BCD to 7-segment display decoder/driver with 30 V open collector outputs
7447 1 BCD to 7-segment decoder/driver with 15 V open collector outputs
7448 1 BCD to 7-segment decoder/driver with internal pullups
7449 1 BCD to 7-segment decoder/driver with open collector outputs
7450 2 dual 2-wide 2-input AND-OR-invert gate (one gate expandable)
7451 2 dual 2-wide 2-input AND-OR-invert gate
7452 1 expandable 4-wide 2-input AND-OR gate
7453 1 expandable 4-wide 2-input AND-OR-invert gate
7454 1 3-2-2-3-input AND-OR-invert gate
7455 1 2-wide 4-input AND-OR-invert gate (74H version is expandable)
7456 1 50:1 frequency divider
7457 1 60:1 frequency divider
7458 1 2-input & 3-input AND-OR gate HC/HCT
7459 1 2-input & 3-input AND-OR-invert gate
7460 2 dual 4-input expander
7461 3 triple 3-input expander
7462 1 3-2-2-3-input AND-OR expander
7463 6 hex current sensing interface gates
7464 1 4-2-3-2-input AND-OR-invert gate
7465 1 4-2-3-2 input AND-OR-invert gate with open collector output
7468 2 dual 4-bit decade counters
7469 2 dual 4-bit binary counters
7470 1 AND-gated positive edge triggered J-K flip-flop with asynchronous preset and clear
74H71 1 AND-or-gated J-K master-slave flip-flop with preset
74L71 1 AND-gated R-S master-slave flip-flop with preset and clear
7472 1 AND gated J-K master-slave flip-flop with asynchronous preset and clear
7473 2 dual J-K flip-flop with asynchronous clear HC/HCT
7474 2 dual D positive edge triggered flip-flop with asynchronous preset and clear HC/HCT
7475 2 4-bit bistable latch HC/HCT
7476 2 dual J-K flip-flop with preset and clear
7477 1 4-bit bistable latch
74H78 2 dual positive pulse triggered J-K flip-flop with preset, common clock, and common clear
74L78 2 dual positive pulse triggered J-K flip-flop with preset, common clock, and common clear
74LS78 2 dual negative edge triggered J-K flip-flop with preset, common clock, and common clear
7479 2 dual D flip-flop
741G79 1 single D-type flip-flop positive edge trigger non-inverting output
7480 1 gated full adder
741G80 1 single D-type flip-flop positive edge trigger inverting output
7481 1 16-bit random access memory
7482 1 2-bit binary full adder
7483 1 4-bit binary full adder
7484 1 16-bit random access memory
7485 1 4-bit magnitude comparator HC/HCT
7486 4 quad 2-input XOR gate HC/HCT
741G86 1 single 2-input exclusive-OR gate
7487 1 4-bit true/complement/zero/one element
7488 1 256-bit read-only memory
7489 1 64-bit random access memory
7490 1 decade counter (separate divide-by-2 and divide-by-5 sections)
7491 1 8-bit shift register, serial In, serial out, gated input
7492 1 divide-by-12 counter (separate divide-by-2 and divide-by-6 sections)
7493 1 4-bit binary counter (separate divide-by-2 and divide-by-8 sections) HC/HCT
7494 1 4-bit shift register, dual asynchronous presets
7495 1 4-bit shift register, parallel in, parallel out, serial input
7496 1 5-bit parallel-in/parallel-out shift register, asynchronous preset
7497 1 synchronous 6-bit binary rate multiplier
741G97 1 configurable multiple-function gate
7498 1 4-bit data selector/storage register
7499 1 4-bit bidirectional universal shift register
74100 2 dual 4-bit bistable latch
74101 1 AND-OR-gated J-K negative-edge-triggered flip-flop with preset
74102 1 AND-gated J-K negative-edge-triggered flip-flop with preset and clear
74103 2 dual J-K negative-edge-triggered flip-flop with clear
74104 1 J-K master-slave flip-flop
74105 1 J-K master-slave flip-flop
74106 2 dual J-K negative-edge-triggered flip-flop with preset and clear
74107 2 dual J-K flip-flop with clear HC/HCT
74107a 2 dual J-K negative-edge-triggered flip-flop with clear
74108 2 dual J-K negative-edge-triggered flip-flop with preset, common clear, and common clock
74109 2 dual J-Not-K positive-edge-triggered flip-flop with clear and preset HC/HCT
74110 1 AND-gated J-K master-slave flip-flop with data lockout
74111 2 dual J-K master-slave flip-flop with data lockout
74112 2 dual J-K negative-edge-triggered flip-flop with clear and preset HC/HCT
74113 2 dual J-K negative-edge-triggered flip-flop with preset
74114 2 dual J-K negative-edge-triggered flip-flop with preset, common clock and clear
74116 2 dual 4-bit latch with clear
74118 6 hex set/reset latch
74119 6 hex set/reset latch
74120 2 dual pulse synchronizer/drivers
74121 1 monostable multivibrator
74122 1 retriggerable monostable multivibrator with clear HC/HCT
74123 2 dual retriggerable monostable multivibrator with clear HC/HCT
741G123 1 single retriggerable monostable multivibrator with clear
74124 2 dual voltage-controlled oscillator
74125 4 quad bus buffer with three-state outputs, negative enable HC/HCT
741G125 1 buffer/line driver, three-state output with active low output enable
74126 4 quad bus buffer with three-state outputs, positive enable HC/HCT
741G126 1 buffer/line driver, three-state output with active high output enable
74128 4 quad 2-input NOR line driver
74130 4 quad 2-input AND gate buffer with 30 V open collector outputs
74131 4 quad 2-input AND gate buffer with 15 V open collector outputs
74132 4 quad 2-input NAND Schmitt trigger HC/HCT
74133 1 13-input NAND gate
74134 1 12-input NAND gate with three-state output
74135 4 quad exclusive-or/NOR gate
74136 4 quad 2-input XOR gate with open collector outputs
74137 1 3 to 8-line decoder/demultiplexer with address latch HC
74138 1 3 to 8-line decoder/demultiplexer HC/HCT
74139 2 dual 2 to 4-line decoder/demultiplexer HC/HCT
74140 2 dual 4-input NAND line driver
74141 1 BCD to decimal decoder/driver for cold-cathode indicator/Nixie tube
74142 1 decade counter/latch/decoder/driver for Nixie tubes
74143 1 decade counter/latch/decoder/7-segment driver, 15 mA constant current
74144 1 decade counter/latch/decoder/7-segment driver, 15 V open collector outputs
74145 1 BCD to decimal decoder/driver
74147 1 10-line to 4-line priority encoder HC/HCT
74148 1 8-line to 3-line priority encoder
74150 1 16-line to 1-line data selector/multiplexer
74151 1 8-line to 1-line data selector/multiplexer HC/HCT
74152 1 8-line to 1-line data selector/multiplexer
74153 2 dual 4-line to 1-line data selector/multiplexer HC/HCT
74154 1 4-line to 16-line decoder/demultiplexer HC/HCT
74155 2 dual 2-line to 4-line decoder/demultiplexer
74156 2 dual 2-line to 4-line decoder/demultiplexer with open collector outputs
74157 4 quad 2-line to 1-line data selector/multiplexer, noninverting HC/HCT
74154 1
7468 2 dual J-K flip-flop with asynchronous clear multiplexer
749.org/wd> 2 dual J-K flip-flop with asynchronous clear HC/HCT
7468 2 dual J-K flip-flop with asynchronous clear
74r/demul-K flip-flop with asynchronous clear HC/HCT
7468synchronous 6-bit bin6>dual D flip-flop
74td>synchronous 6-bit bin-bit binary counters 49fil2 2 dual 4-input NAND gate with op1ip-flop with dual J
741G80 1 49fil2 4 dual J<2 dual 6 4 2 dual J-K flip-flop with asynchronous clear HCt latch dual tive-edwd> 2 dual J-K flip-flop with asynchronous clear HC/HCT
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748d>1 4-bit bidirectional unived>dual D flip-flop
748d>1 49.org/wd> 2
qa8 enetd>si>dual J-K flip-flop with asynchronous clear BCD to decimal decoded> gated ltodi.cialips.pttd>b-dtd>hrel teclasss/TTLpivee9www.nxp.com/documentsFn.wikipedia.org/wiki/Full_adrandom access memory 2 7468synctK flip-flop with asynchronous clearHC/HCT
7499 1 4-bit bi monostable multivibrator with clear > r> 74td>741/74HC_H monostable multivibrator with clear r
r>
74td>741/74HC_H monostable multivibrator with clear HC/HCT
7499 1 4-bit bi monostable multivibrator with clear
7499 1 49.org/r>
HC/HCT
4
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2 dual 4-input NAND gate with op2 collector outputs 4 2 dual21ead-only memory 4 1 single r2 dual 4r/demul-K flip-flop with asynchronous clear multivibrator
FIFO (d fHC/HCT
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4 6 hex noninverters with op23follow">HC/follow">HC/oc85 1 4
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4 1 HC 1 HC/HCT 1 4 HC/follow">HC/oc85 -line to de6 4 HC/oc85 -line to de6 4 HC/oc85 -line to de6 4
7447 1 BCD to 7-segment decoder/drivte flip-flop with asynchronous clear HC
7447 1BCDPull-upnt decoder/drivte flip-flop with asynchronous clear
7449 1 BCD to 7-segment decoder/driver with op2ne priority encoder quadt decoder/driver with op2nbit bistable latch
74152 1 dual Jiv748
4 HC/HCT 2 dual 2coder/demultiplexer 2 dual 2c collector outputs
74157 4 quadt/td> -line to de6 4 4 HC/HCT iki/Ded>74100 te flip-flop with asynchronous clear multiplexer
synchronous 6-bit bi2sing interface gates 748
7431 6 dual J-K
2
O BCD to 7gered J-K HC/t latch 4 2 dual 4-input NAND gate with op2ip-flop with preset 2 dual 4-input NAND gate with op2i3-flop with preset 49.org/wd> 2 <_t/tdg>W
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